1. Field of the Invention
The present invention relates to a method for managing electronic circuit design data.
Recently, there has been the following increased demands in the development of electronic circuit devices.
(1) There is a trend in an increase in the circuit scale of devices, down-sizing of devices and an improvement in the performance of devices. For example, full-custom LSI devices and MCM (multi-Chip Module) devices have been developed as devices on the above trend. Normally, a hierarchical-layer module design has been employed to achieve such devices, which have a very complex hierarchical-layer structure. In order to realize the high-quality design based on interchangeability in the overall device, it is necessary to analyze and evaluate the design from viewpoints in which the designed hierarchical structure is seen through. Hence, it is required to provide a design data management function capable of integrally managing design data having different lengths in each of the designed hierarchical layers even when the design data should be originally managed in each of the hierarchical layers or originally includes items to be managed in each of the hierarchical layers.
(2) The development of electronic circuit devices is very competitive in order to market higher performance devices in advance of competitors. Hence, nowadays concurrent engineering has been employed in which various design works necessary for the development of devices are concurrently promoted. Examples of these design works are mounting design, a delay time analysis, thermal analysis, test design and so on. In order to perform the concurrent engineering, it is required to efficiently manage a plurality of design versions of a single design object in a period of time. That is, it is required to provide the function of managing the histories in processing of a variety of design data and of easily and efficiently recovering old data.
(3) It is required to follow various needs in the market by efficiently managing different versions of mounting design data with respect to identical circuit design data. That is, it is required to additionally manage different versions of design data having different contents with respect to one basic design data.
(4) The description of the content of the design is not given at the logic gate level but at the high-class description language level corresponding to the operation level under the circumstance in which there are demands of improvements in the quality of electronic devices (in views of parameters such as functions, performance, reliability), an increase in the circuit scale and a reduction in the time necessary for the development. The logic gate level design description can be efficiently generated by using an automatic logic synthesis function. Hence, the following function of managing the electronic circuit design data is needed. That is, the function is needed which simultaneously manages a description of the operations of designed parts in the module design is given by the logic gate level design description and the high-class description language. Further, the function is needed which is capable of providing all possible combinations of arbitrary description levels depending on the objects when handling the overall device.
(5) The development of the following distributed design process is required. That is, the whole design data of the target device is managed by a host computer, while engineering workstations which have recently become popular are used. In this case, the high performance and the graphic function of the workstations are positively unitized to provide the appropriate design environment. Hence, it is required to efficiently manage how the design work is distributed to the workstations. For example, which parts of the design module are handled by the workstations.
(6) There is an increased complexity in the design and analysis works with respect to the layout design of full-custom LSIs or a validation of a logic design including macrocells in which only the timing or function level is known. Under the above situation, a group of CAD (Computer-Aided Design) tools cannot handle all of the design work because the group of CAD tools are developed under the condition that all works are based on consistent interfaces. Hence, it is required to provide CAD tools developed under the assumption of use of different interfaces. It is necessary to apply design data to the CAD tools capable of handling the different interfaces and to feed back the design results to the input sides of the CAD tools.
(7) In order to efficiently accomplish the high-quality design matching the complexity and advance in the design conditions under the LSI technologies, it is required that the designer inputs a design target or intent regarding a particularly design part or use different design restriction conditions with respect to a partially identical design element. Hence, even in the management of design data, it is required to manage the design target, the design intent and the design restriction and apply information concerning the above matters to the CAD tools for use in supporting of design/analysis, so that the design and analysis can be finely supported.
2. Description of the Prior Art
FIG. 1 is a diagram of a printed circuit board in which LSI chips are used as sub-modules. A printed-circuit board 50 has external terminals (1), (2) and (3), and three LSI chips LSI.a, LSI.b and LSI.c mounted on the printed-circuit board 50. Numerals in circles denote input or output terminals of the LSI chips, and symbols .alpha., .beta., .tau. and .delta. denote interconnections (nets) connecting the input/output terminals of the three LSI chips and the external terminals (1), (2) and (3) of the printed-circuit board 50.
FIG. 2 is a conventional method for managing electronic circuit design data regarding the printed-circuit board shown in FIG. 1. The method shown in FIG. 2 includes a first hierarchical layer 61, a second hierarchical layer 62, and a third hierarchical layer 63. The first hierarchical layer 61 describes the structure of the printed-circuit board design data. The second hierarchical layer 62 describes the structure of LSI design data. The third hierarchical layer 63 describes the structure of in-LSI layout/block design data. The numerals and symbols (1), (2), (3), a, b, c, .alpha., .beta., .tau., and .delta.1 through 5 placed in circles correspond to those shown in FIG. 1.
The first layer 61 describing the structure of the printed-circuit board design data manages printed-circuit board title data 611, printed-circuit board external terminal data 612, mounted-LSI data tables 613, a mounted-LSI input/output terminal data table 614, an on-printed-circuit board interconnection data table 615, and a database access unit 616. The printed-circuit board title data 611 stores data which represents the overall printed-circuit board. The printed-circuit board external terminal data 612 stores data regarding the external terminals attached to the printed-circuit board. The mounted-LSI data table 613 stores the design data of the LSIs mounted on the printed-circuit board. The mounted-LSI input/output terminal data table 614 stores data regarding all the input/output terminals attached to the printed-circuit board. The on-board interconnection data table 615 stores data regarding the shapes of the nets formed on the printed-circuit board. The database access unit 616 indicates the size of data of the minimum unit accessible to the database.
Further, a group of an operation describing test 617 and net wiring figure (pattern) data 618 is managed as particular (exclusively used) data. The operation describing test 617 describes the operations in test format. The net wiring pattern data 618 is length-undefined data which is not suitable for management of arrangements.
In FIG. 2, the printed-circuit board external terminal data table 612, the mounted-LSI data table 613 and so on are managed for each hierarchical layer in table format by a database which manages data in table format such as a relational database. For example, in the printed-circuit board external terminal data table 612 is managed so that data can be individually accessed for each design work while keeping the correspondence with the table as in the case of a logic design attribute table, a mounting design attribute table, a text design attribute table and so on. The logic design attribute table indicates which logic levels of signals are applied. The mounting design attribute table indicates connections when mounting parts. The test design attribute table indicates states to be set when testing the circuits.
More particularly, the logic design attribute table, the mounting design attribute table and the test design attribute table manage the following data.